Replies to post #661 on Advanced Micro Devices Inc (AMD)

[sgolds]

neye_eve, on HT links, from memory I recall that the PCI controller is daisy-chained onto the I/O controller. To dedicate an HT link to PCI would be wasteful of the resource - PCI bandwidth is way less than HT.

Actually, I just found the definitive document. Look at slide 19 - legacy PCI is hung off of the 8111 HT I/O hub, using only a single HT link for all I/O (except DRAM, of course). Note that this is a Clawhammer configuration, there is only single channel DDR:

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Computex_Press_Presentation_FINAL1.p...

[CombJelly]

neye_eve, RE: Hammers and HTT.

Remember that HTT comes in two flavors, regular and extra-spicy (cHTT). Now cHTT differs from HTT in that it is faster and probably has some extra lines for cache coherency, but I don't think cHTT has been publicly documented yet. From the sample layouts that AMD has been waving around, cHTT can be used as a regular HTT port. From a low end dual processor system AMD had diagrammed, I suspect that all of the HTT ports on Hammers can operate as a cHTT, but again, there isn't any public information on this...

Another thing that can be done with HTT ports is that you take take a single 16 bit port and use it as 4 4bit ones, 2 8 bit ones or a single that is 16 bits wide.