Re: Post this very long list. And a link to an Intel statement of a longer pipeline for Merom as well.
They did a slide of this at last IDF. You can probably do the research better than Wouter. Try Anandtech, I think I remember them showing something on it.
Please don't gaggle only, lay eggs: Post this very long list. And a link to an Intel statement of a longer pipeline for Merom as well.
Intel announced this so far:
- 64 bit extensions - Four issue design - 14 stage pipeline* - Improved (bandwidth aware) prefetch - Deeper buffers - Direct L1-to-L1 cache transfers - Higher L2-core bandwidth - Memory disambiguation - Macro-op fusion - Power management up to individual execution units
But there's probably a lot more in *T-terms. IOAT and Rockton come to mind. Also I expect better RAS features and a L3 cache controller for MP server versions. Anyway, you don't need this whole list. The 32-bit to 64-bit transition alone already makes it a new core.
* Current generation Pentium M core is said to have 12 stages. The exact number is a secret but several reports say "extended to 14 stages".