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wbmw

10/20/05 7:29 PM

#63968 RE: kpf #63965

Re: Prescott vs. Northwood?

It amazes me that people can continue to confuse the gain in Prescott's power with a faulty process, in spite of all the discussion from countless people who know better, as well as the substantial amount of data from Dothan in how the same process can be used to reach higher performance and lower power on a more power efficient design.

Northwood was a 20-stage pipeline CPU, and Prescott is a 31-stage pipeline with a large amount of additional logic aimed at topping 5GHz clock speeds, but due to the power wall, it didn't even hit 4GHz. This was a 20% miss to expectations, and it has no likelihood of happening again with Dempsey or Presler, since both of these are simple shrinks of the 90nm equivalent.

Time to update your notes or whatever you have to do, because rehashing this well known explanation is the most useless form of forum usage I can think of.
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chipguy

10/20/05 8:37 PM

#63980 RE: kpf #63965

process shrinks *undeniably* offer improvements in performance and/or power.

Umm. Prescott vs. Northwood?


They are very different designs. Had Prescott been
implemented in 130 nm like Northwood it would have
been bigger, slower and hotter than it was. That is
the benefit of the process shrink.

OTOH, Dothan and Banias are far more similar in
design so the shrink benefit is overtly obvious.