Replies to post #316 on Advanced Micro Devices Inc (AMD)

[spokeshave]

Elmer: Re: SOI

The consensus is that moving to smaller geometries is just not possible on bulk silicon alone. The RC constant of the substrate just gets too high. AMD chose to tackle the problem by attacking the capacitance part of the equation with SOI. It's probably not completely necessary for 130nm, but it is completely essential for 90nm.

Intel, on the other hand has chosen to attack the resistance part of the RC equation. It will be doing that with strained silicon. All of the arguments you just made about AMD and SOI apply to Intel and SS. Neither strategies are risks, per se, they are absolute essentials in order to achieve smaller geometries. As SOI was AMD's "hail mary", so will strained silicon be Intel's "hail mary". They will also be adding lok-k to the mix at the same time. So, make that a hail mary in the pouring rain.

While you have been patting yourself on the back for how prescient you (and about a gazillion other people) have been about the pitfalls of SOI, I have been predicting that SS for Intel will prove to be similarly problematic. I guess the big difference is that Intel can throw gobs of money at the problem. We'll see if that's enough.

[CombJelly]

Elmer, RE: SOI and AMD.

I think at least some of the motivation for SOI was in reaction to the criticism about the power draw of the TBird.