Replies to post #4278 on Intel Corp (INTC)

[spokeshave]

I'm confused. Why would chipsets be speedbinned at all? Chipsets run at two speeds - the PCI bus speed and the FSB speed. There is one speed bin for the northbridge (200 MHz) and one for the southbridge (33 MHz). What other speeds would be "binned". I don't get it.

[Elmer Phud]

Dew -

Why hasn’t speedbinning previously been done for chipsets?

Traditionally, chipsets have been manufactured at Intel on second generation process technology, with second generation manufacturing all the way thru the system. That doesn't mean second rate quality. This was the way that Intel made use of technology that was no longer cutting edge but already depreciated while still being usefull for non speed critical application. Designs were always targeted to yield 100% to the target speed, but I've always wondered why this restriction needs to be enforced. Speed binning isn't that big a deal. The actual speed determination is a relatively small part of the total test. If it doesn't pass the speed test at high speed then slow it down and try it again, then bin it out accordingly. Some other controls need to be in place but with Intel's volumes of 100s of Millions of chipset devices it can be put in place. Pretty elementry. I think it is long overdue. When you think about it, why restrict yourself to requiring that 100% of the functional units all meet the same speed when you can raise your target and get some binsplit to the higher performing part? If it makes sense for Processors then why not for Chipsets? You've lost nothing whatsoever because you only need to require that 100% of the units meet the lower speed. The higher speed part is pure gravy. If a higher speed Processor demands a premium then the chipset should too, espically if it provides the same over all performance improvement as a speed notch at the Processor level. The 875 seems to do this.

EP