Replies to post #57289 on Advanced Micro Devices Inc (AMD)

[chipdesigner]

Joe, that sounds like quite the change. If it comes in Q106 on the new socket, I wouldn't be surprised at a more straightforward 4 core setup, especially if it is on 65nm, assuming the new socket provides enough bandwidth.

4 x (512K L2 + L1 + core) + HT/IMC/XBAR on 65nm should be about:

.58 * ( 2 x 147 ) - 5% (or so) = 161mm^2, assuming no L2 cache density improvement.

On 90nm: 280 mm^2.

With 1MB L2 per core:

.58 * (2 x 199) - 3% = 224 mm^2, large but doable on 65nm. A crazy 390mm^2 at 90nm.

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If they can pull off a shared cache, that would be nice, though.