Replies to post #55900 on Advanced Micro Devices Inc (AMD)

[fastpathguru]

Again with the focus on my use of the word "glueless," like it matters.

I've stated multiple times that yes, the term "glueless" literally means no extra logic. Yes, you could call my original use of the term "sloppy", lacking qualification re: scalability.

If you were a nit-picker, and had nothing more substantial to attack.

Xeon DP is glueless from 1 to 2 sockets and Xeon
MP is glueless from 1 through 4 sockets. IMO there is nothing
open to debate, redefinition of well understood technical
terminology by sloppy wannabe computer engineers not
withstanding.

That Opteron's implementation of "glueless" is superior to Intel's is similarly not open to debate.

fpg

[pgerassi]

Dear Chipguy:

Your "glueless" design has some flaws, if it requires any other chip to tie them together. "Glueless" is not defined as from N to N+1 for any N, but from M to M+1 for all M between 0 and N-1. That is a big difference.

By your definition any cluster is "glueless" just because I can add a CPU to any node's MB. Even a Horus based system would be considered "glueless" (just think of going from 5 way to 6 way) by your definition. And many consider any system using Horus as needing "glue". That includes myself and probably even you. That is why it must be for each and every value of M between 1 and N-1.

You need the glue to get M=0 in all Xeon/Pentium/Itanium systems. If those Xeons were like PCI bus masters, you could say that Xeon was "glueless". They need no other glue logic to intercommunicate. For Coax Ethernet, it is glueless, but 10/100/1000BaseT Ethernet requires either a hub or switch beyond N=2, which means it needs "glue" (N=2 is made by a simple mirrored cable and N=1 is just a disconnected NIC). For Opterons, N can be 1-8 and be truly "glueless".

Pete