Re: more links on Google referring to the "glueless" Xeon:
Good point. Glueless isn't really the issue. But there clearly is a diffence between the Xeon/Itanium and Opteron architectures, because (unless you support it with "glue" chips) Xeon's bandwidth actually drops as you add CPUs because as you add CPUs you add nodes to a single buss, forcing it to run more slowly.
Xeon was 1066mhz FSB single chip, 800mhz dual, and 400mhz quad, (all x64) and that single bus has to handle all memory and all I/O accesses for all chips. Making a Xeon architecture chip dual core doubles the load on the buss, dropping all I/O and memory speeds down to the next notch.
Opteron's FSB is it's I/O buss, and that stays at 2000mhz (x16) all the way up 8 CPUs. Additionally, Opteron supports a second full speed I/O buss. On top of that, for each Opteron added, 2 400mhz (x64) memory chanels are added, and on top of that going to dual core in the Opteron architecture doesn't slow down the buss.
That's why far less expensive Opteron systems out-scale extremely expensive Itanium and Xeon systems, and they do so even though they have as little as 1/6 the (expensive to produce) cache.
In other words, I agree that we can't differentiate the Xeon/Itanium architecture from the Opteron architecture by calling one "Glueless" and the other other "not Glueless."
How about calling the Xeon/Itanium architecture "crippled for SMP" and the Opteron architecture "not crippled for smp?"
Is that better?
:-)
The spec scores where a single Itanium is a little faster in floating point (while still being slower in integer) than a single Opteron, but a 4-way (dual core) Opteron beats an 8-way Itanium in pretty much all tests, are particularly eye-opening.
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