No, you're wrong.
I am in a charitable mood today so I will toss you the
clue you are so *desperately* in need of.
Transistor performance in a digital circuit depends
on gate overdrive, the difference between the high
or "1" voltage level and the transistor threshold
voltage. The threshold voltage gradient across a
large dual core chip is on the order of a few mV or
less. But an MPU is a very noisy environment with
fluctuation and cross die differences on the power
rails from IR drop and inductive effects driven by
di/dt are on the order of hundreds of mV.
Like I said, process variation across the CPUs in
a CMP chip is in the noise.
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