Replies to post #921 on Intel Corp (INTC)

[Yousef]

Fish,

Re: "How much, if any, will this retard scaling?"

Really depends on your critical speed path circuits and whether they
are speed limited by gate loading or interconnect loading. Most LowK
materials give a theoretical reduction in capacitance of >25%. However,
when a Lowk process is actually implemented with Si3N4 (silicon nitride)
etch stop layers, TEOS capping layers, etc ... The actual benefit of LowK
drops to <15% change in capacitance. Again, it will also depend on the nature of the
critical speed path as well.

Make It So,
Yousef