Replies to post #3563 on Rambus (RMBS)

[cordob]

Ha Calbiker, I knew you were an oldie:)

Ha; calbiker used it in the seventies.

The (dma) memory transactions don't go through the cpu in the AMD64, the corssbar switch ahs a similar function to the northbridge in this case (with the advantage that caching can take place at the same time).

Yes I agree it makes the die bigger, but then it has worked apparently, Intel's die are getting bigger because they need all the chache to keep up, LOL:)

Why should video streaming data have to travel through the processor? The added complexity also presents pin limitation problems. Socket 754 processors have only one memory channel. Why?

Pins are cheap apparently, 1000 pins no problem these days. Anyway most applications are perfectly happy with one memory channel.

On the rigidity, yes , to some extent, but the advantage is simpler chipsets (and the IO chipsets go over from one cpu to the other, because it is all HT). I believe a next version will have a FB-DIMM type IO for the memory so that solves that. (multiple ones)

Cheers
Cor



OK enough AMD stuff, my next post is about rambus/PCIe ;-)