Replies to post #46888 on Advanced Micro Devices Inc (AMD)

[dacaw]

SSE2 has a lot of integer too

[Petz]

I suspect if another FP adder were added, its "guts," a 64-bit integer adder, would be available for integer and SSE integer instrucions too. IIRC, SSE3 has simultaneous I+-J also.

Anyway, I hope DDB is wrong that McGrath's enhanced FPU won't be implemented in K8 "E" stepping. DDB did say that cache-to-SSE2 bandwidth would probably double. Even without any extra execution units, that would probably eliminate any Intel advantage in highly Intel-optimized code (think SPEC!), but wouldn't be enough to beat the Power 5.

Petz