Replies to post #44283 on Advanced Micro Devices Inc (AMD)

[DDB]

CJ - "From the way that Paxil(I know I have that wrong) is supposed to operate, this isn't a bad way to do it."

This is true, since the time to get such a chip done, was really short for Intel. And besides the bus inefficiency it will increase performace - compared to a similarly clocked single core P4 - more than HT did.

[fastpathguru]

Aren't the contacts on the die that are attached to the chip package usually arranged around the the die's edges?

It's really simple to photoshop two dice into one package. I'd imagine it's somewhat more complicated to actually realize that vision...

The dual-core pictured would have one edge of each die unavailable for attachment.

The quad-core pictured would halve the available die edge area for package interconnect.

"Intel would be misleading its audience it it tried to fit any other implementation under the dual core label," said Brookwood. "They [the readers] argue further that Intel would not be willing to risk its reputation for high integrity, just for the sake of a product demo at a conference".

Who knows what Intel will do to avoid looking inferior to their competition? They weren't worried about risking their reputation with the band-aid P4EE, or '03 "shipping for revenue" Prescott deal...

I personally wouldn't be surprised in the least if it turned out to be two discontiguous cores packaged together.

fpg