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burn2learn

07/29/04 7:26 PM

#12639 RE: upc #12638

Does this suggest they have no idea if they can make one at all? What would provide confidence of hitting 4 GHz in Q1 05, while knowing they cannot make it in Q404? In other words, is this expressing hope that a new not-yet-evaluated stepping will solve the problem?

Typically there are transistor revs and process developments planned to get to a certain speed grade. These are usually planned to intercept a stepping.

1. speed increase from process + stepping = total goal

The process / transistors revs don't always go per plan and could be that the roadmap items to get to a goal speed improvement did not get expected results or the yield is impacted but they got the results. Either can be mitigated through further experiments or roadmap changes

or the stepping is not ontime, or both of the above



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wbmw

07/29/04 8:08 PM

#12641 RE: upc #12638

UPC, Re: Does this suggest they have no idea if they can make one at all? What would provide confidence of hitting 4 GHz in Q1 05, while knowing they cannot make it in Q404? In other words, is this expressing hope that a new not-yet-evaluated stepping will solve the problem?

No. It means that the stepping they originally scheduled for Q4 either has schedule problems (A), or it's on time but it does not hit the expected frequency (B). Therefore, they are deferring the 4GHz sku until they come out with the planned stepping (scenario A) or they intend for the next stepping to hit the 4GHz frequency (scenario B).

By the way, there are details missing here that could give a clearer picture. For example, Intel may be able to hit 4GHz, but the bin split may only be 5% or 10%, which isn't enough for the judged holiday demand. On the other hand, they could be getting 0% binning at 4GHz, at which point another stepping is required to simply launch anything at all. Therefore, anything else at this point is speculation at best.