Saturn, all you need to remember is that a DP Nehalem will have 2 CSI links (can communicate directly with the other processor and the chipset), while a MP Nehalem will have 4 CSI links (can communicate directly with 3 other processors plus the chipset). These are, indeed, different chips, and have different projects associated with them (DP is Bloomfield, I think, while MP is Beckton). The number of cores per socket is almost irrelevant to this discussion (notice the slides say 'up to' 8 cores); what's important is how many CSI links there are per socket.
If you look at the diagram for the 8-socket system, you'll notice that each socket still only has 4 CSI links. However the difference is that each socket no longer has a one-shot link to every other component; now a "hop" is required in some cases to get data from one component to another. This is an additional layer of complexity in the CSI logic, which is accounted for in the CSI spec, but you can bet that Intel will be focusing on the 'easy' things first like 2S and 4S systems.
The Nehalem demo at IDF was a 2-socket system, so logic would dictate it has 2 CSI links, and will likely be the first Nehalem product. Alan's assumption of an MP Beckton in 2009 seems reasonable to me...
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