Haddock, I have a problem with the thesis that the 'dark transistors' in Prescott would be IA64. As a software guy, I'm going out on a limb here, but we've been hearing all these years about how x86 and IA64 are incompatible. IA64, the world's only implementation of EPIC, relies on an intimate relationship between the compilers, instruction set, underlying microcode and hardware implementation of that microcode. Touch one and the whole thing unravels into a serial mess. (In fact, that has been the whole thesis behind the just wait for better optimized Itanium compilers crowd.)
Now, implementing a hardware IPF layer on top of an x86 microcode doesn't seem workable to me. It is the opposite problem from the compiler problem: Now you take highly optimized IPF code that is meant to be intimately matched to a supporting hardware ediface and suddenly throw it against a totally different microcode design. All the benefits of the compiler optimizations suddenly become irrelevant, and the IPF instructions have to be implemented as a bunch of x86 opcodes. Things that are suppose to happen in parallel suddenly have dependencies on results from each other. Stuff that should be accomplished in a few cycles balloon into literally dozens of cycles.
My sense is that this would work so terribly that not even Intel would consider trying to make it work.
But it would make the x86 emulation in Itanium look good!
:)
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