Replies to post #24201 on Advanced Micro Devices Inc (AMD)

[wbmw]

HM, FWIW, there was a publicized Northwood shrink which brought the die size down from 146mm^2 to 131mm^2. Also, Intel has publicized a Prescott die size of about 113mm^2, but I suspect a mid-life shrink to reduce to to the ~100mm^2 range. This is a very competitive die size as far as silicon costs go.

Lastly, Willamette started at about 220mm^2 with a shrink down to 202mm^2 at mid-life.

[j3pflynn]

HailMary - re:"I always assumed more transistors for Intel's cores because of the larger die size (compare Barton to Northwood). I was wrong there."
Different # of layers is probably the biggest thing that gotcha there.
Paul

[sgolds]

HailMary, others, transistor counts and power dissipation - I'm not sure how much we can learn from that. The reason is that Intel and AMD process now differ so much from each other that direct comparison is difficult.

What would happen if they were on the same process? One can't take AMD's 90nm K8 design and put it on Intel's 90nm P4 process (or vice versa) since the gate design is highly dependent on process. So such an experiment can't even be attempted.

How about comparing overall performance and then subtracting the power consumption of cache, interfaces and the K8 memory controller? This would give us a comparison of the power consumption of the cores of two similarly performing processors. Unfortunately, this also fails to illuminate because so much of the performance of the two companies' designs depend on cache, interfaces and the K8 on-board memory controller.

HailMary, this is really a post about the futility of these power arguments relative to high vs. low IPC. I am not aiming specifically at your argument, I only chose to respond to your message because you spent them most work trying to come up with a reasonable method to resolve it.

Intel and AMD are taking very different approaches to desktop and server x86 design. We will only know which method is better in hindsight - will AMD need to increase instruction cache length to support faster clock speeds? Will Intel have to give up on the low IPC approach and base future desktops & x86 designs on a Dotham approach?

I just don't see a good way to predict how this will play out. Good, well informed engineers at Intel and AMD also differ on this, so I'm not surprised this board can only nibble around the edges of the problem.