Re: I was very clear on this already.
1. Intel said it will be three fabs in 45nm until recently.
2. Then it announced metal gates in this node, and by the same time changed communication to four fabs.
Not more - not less.
Perhaps you should consider the fact that the timing of Intel's public announcements doesn't necessarily coincide with the timing of Intel's internal revelations. I have already asked you to consider whether Intel may need the fab space for new products. You have not commented on this proposal.
Maybe you consider it too outlandish that Intel would ever need more wafer starts for a product that allows them to enter the discrete graphics business, much less a business that attempts to sell into low cost emerging markets. I am speaking of course of what we know so far of Larrabee and Silverthorne. Do you think that Intel should plan for failure with these new products, and make sure their capacity does not grow from 65nm...? That seems to be implied in your theory that the 4th 45nm fab is just a means to account for yield loss.
Re: Besides, metal gates are known to be a manufacturing challenge. The relevant publications are not publicly available on the net, at least not without subscriptions. So I cannot link to these.
Intel has demonstrated products using HK/MG, and others can't seem to deliver publications. That tells me that perhaps Intel is having more success with this complicated process than their competitors. In fact, perhaps they have also solved the yield and manufacturability issues that are plaguing their competitors.... I know it seems outlandish, but it's just a theory....
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