Re: What is concerning though for AMD IMO, is limited to non-existant IPC gain over K8...
I really don't think that POV-Ray is the best example of what Barcelona IPC will deliver. It's heavily floating point with SSE support limited to non-existent, and doesn't require much in the way of memory bandwidth. It already scales almost linearly with respect to core count and frequency using existing architectures. Since Barcelona's enhancements came in the form of integer and SSE instructions, along with memory bandwidth and latency optimizations, that is why you won't see much of a benefit here.
I suspect on other applications, you will see a 5-15% benefit in integer apps, and as much as a 20-40% benefit on SSE tuned apps. This will help it to catch up to Core 2 in many benchmarks, but as I've suggested before, I really don't expect it to take the lead.
In server apps, the memory bandwidth and latency optimizations will help it further compete with Clovertown, and while I expect to see some victories, I hardly expect to see a close-out. It will excel in HPC apps, though, probably winning most of these.
In MP servers, it will easily trounce Tulsa, and probably beat Tigerton in the majority of apps. Intel needs to get Tigerton to market and ramp quickly to hold at least half of the MP server market. I see AMD using Barcelona and later Shanghai to capture as much as 50% of this market, since Intel will be disadvantaged until they get to CSI.
In nearly every other market, I think Barcelona will be disappointing.
Re: Good point, but if Barcelona only clocks at 1.6 GHz at 65W, and they wanted to make a comparison at the same clock speed, that's what probably lead to the selection.
I seem to recall that Barcelona will clock to 1.9GHz in the HE configuration, which puts current demos still below launch speeds.
But there is still the question of why they would demo HE parts if power efficiency was not an over-arching message in the demo. Their primary message was dual core to quad core scalability. And for that, it would make more sense to use the fastest cores available.
I suspect that 1.6GHz is currently the fastest core available for AMD on the current stepping. If they really do have a B-step that clocks much higher, they haven't shown it. And why wouldn't they, unless A) it doesn't exist, or B) it has major issues.
In the case of A), AMD seems screwed in terms of frequency. I happen to strongly believe they will launch in the 2.xGHz range, but getting to 2.3GHz may yet be a challenge for them. In the case of B), they'll need to step the part yet again, which puts pressure on the schedule. In the case of C), which many may claim entails the possibility of AMD sandbagging, this would be pretty weird. The logic behind C) is that AMD doesn't want to let the competition know how good they are until they launch. If this is the case, then AMD is more stupid than we've all given them credit for. Not only are they screwing their public image by holding back the goods, but they are doing nothing to change Intel's execution. It's not like Intel is going to get complacent enough that they will cancel Nehalem, or delay Penryn, just because AMD is showing piss poor demos....
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