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chipguy

11/30/03 7:08 PM

#19012 RE: Dan3 #19008

Pay particular attention to the two slides at the bottom of page one that show how three instructions are sent to the three cores.

http://www.lems.brown.edu/~iris/en291s9-02/lectures/Eric-Itanium.pdf


That is the instruction bundle format of IA64. It has
nothing to do with "cores". Don't use terms you are
completely clueless about, like "cores" apparently,
unless you don't mind appearing completely foolish as
in this case.
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Not a Short

11/30/03 9:16 PM

#19018 RE: Dan3 #19008

Dan3, please beleive me when I say that I am not anti-AMD or pro-Intel.

Please also believe me when I say there is nothing on page 1 of that PDF that makes me think or beleive that there are 3 actual cores or imply that they merged 3 core designs.

I suggest you look at page 3 of the PDF in the box labeled IA-64 Hardware model, specifically where it says "parallel resources". It lists:

4 integer
4 mmx units
2+2 FMACs
2 load/store units
3 branch units
32 entry ALAT

Now look at the next box (down and to the left) called Itanium Processor Model

Both seem to cover the same basic set of "components". Do you see signs of 3 cores? Physically it doesn't look like 3. Logically it looks like one straight line (see the hardware model with arrows going straight through from left to right), logistically it looks like a diagram of a database (is that a many to many connection from the L1 to L2 cache?).

I just don't get what made you say "the three cores"