$GTCH Filed a Non-Provisional Patent Application Seeking to Protect the Automatic Correction of Integrated Circuits Connectivity Mismatches
SAN DIEGO, Aug. 16, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. ( OTC PINK: GTCH ) ("GBT” or the “Company”) filed a nonprovisional patent application for automatic correction of Integrated Circuits (IC) electrical connectivity mismatches system and method. The application was filed on August 3, 2022, with an application # 17880055. The nonprovisional patent application seeks to protects programmatic methodologies and algorithms to automate ICs electrical connectivity mismatches correction to achieve faster and more efficient designs, particularly for advanced nanometer range of 5nm and below. An IC design flow consists of a few stages which involve software tools to architect, capture, simulate and verify the IC’s correctness within a few fields. These computer-aided-design (CAD) programs, also called Electronic Design Automation (EDA) tools are key components in transforming a product’s definition and circuit concept into production-ready IC design. A Layout-Vs-Schematics (LVS) Verification program) is an integral part of the IC’s signoff process to compare the electrical connectivity (wiring) of an IC layout against its schematic diagram. A connectivity mismatch would mean there is a mistaken wiring connection between the electronic components and may lead to a non-functional chip’s circuit or wrong electrical outcome. Typically, in custom and semi-custom analog, mixed and RF layout styles, these corrections must be done manually which takes a significant amount of time.
GBT’s nonprovisional patent application seeks to protect an algorithmic systems and method to perform an automatic LVS correction with a click of a button. The system will read the IC’s schematic and layout data, compare their electrical connections (wiring) and in case of mismatches detection, disconnect the faulty wires and re-route them in the layout to create a correct electrical conductivity. The goal of the system is to Auto-Correct the layout, without causing any LVS, geometrical (DRC), Reliability Verification (RV), and Design for Manufacturing (DFM) violation. GBT already started research in this domain and plans to expand it during 2022.
“We predict there will be global growth in the semiconductor arena in the next decade. A $52 billion bill is waiting for President Biden to sign, major IC fabrication corporations have started to build IC manufacturing plants in the US, and major R&D efforts are constantly on the rise by IC design firms. GBT is investing in microchip’s productivity tools especially for advanced nodes. As major physics obstacles are approaching with small nodes, like 5nm and 3nm, there is a major demand for programmatic solutions to assist with the design and manufacturing these advanced ICs. Advanced design automation solutions will be the key to produce advanced nodes chips in reasonable amount of time. GBT has identified weak spots and bottlenecks within IC layout and backend design arena and investing vast efforts to provide algorithmic solutions to address these challenges. One of the major ones is the LVS domain. Our nonprovisional patent application seeks to protect an automated LVS correction system to analyze an entire chip data, checks for electrical connectivity mismatches and Auto-Corrects them with a click of a button. The correction process will be involved with identifying existing mismatches connections, disconnect them, and re-route correctly. This technology includes hierarchical auto-correction and other advanced nodes features. Its a huge challenge to perform such an operation programmatically and we are using our AI technology to manage the vast amount of data processing, performing the challenging mathematical analysis, concluding possible solutions and execute the auto-correction. The IP includes a neural networks and advanced algorithms to achieve these functionalities in a very short time, which may take days or weeks to fix manually. This goal of this technology is to introduce another GBT innovative design productivity enhancement tool, enabling IC design firms’ significant reduction of their overall projects design time and bring their microchips faster to market” stated Danny Rittman, the Company’s CTO.
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