- bulk vs SOI
Here things change month by month. Based on the ramp rates we are seeing projected by the motherboard makers for Q1 and Q2, AMD must have substantial improvement in their SOI yields by now.
SOI wafers are more expensive, the implanted layer causes
higher scrappage, higher dislocation density, higher defect-
ivity, greater parametric variation, and ultimately lower
yield. AMD can improve its SOI process over time but it will
never close the gap with bulk.
- 6 vs 9 layers of interconnect
That will add time to the manufacture of A64, I agree.
It also increases wafer processing cost and lowers yields.
Each extra metal layer involves several lithographic steps
with many processing sub-steps and each one is an opportunity
for a mishap to occur or defects to creep in.
OK, a little more costs for the extra pins. Is this significant?
Yes. Packaging costs is an appreciable fraction of the cost
of a finished working processor.
What differences in test costs?
The HT operate at data rates twice that of the fastest P4
pins. Tester cost, and therefore test time cost per hour,
goes up dramatically with peak pin electronics speed. The
HT link likely involves much greater analog content for
CDR and related circuitry and process compensation than a
sub GHz FSB and this will tend to drive up test time.
It all works out OK.
It does for Intel. Its uP margins are closing in on the 60%
level. OTOH AMD's costs will rise dramatically as its product
mix switches from K7 to K8. Can AMD's ASP rise fast enough to
keep its already low margin from sinking? I suspect Q4 will
be good for AMD, it might even show a profit. But once the
Prescott starts shipping in volume in 1Q04 it will be back
to the same old same old for AMD.
News 
Market Data 
Discover 
AI
