Replies to post #6203 on AMD strictly moderated (AMD)

[chipguy]

On second thoughts about it, a single-die NB/SB chipset solution should ease pad-limitations: No i/o pads required to connect the two chips.
However, AMD still plans for a two-chip-solution for its 7xx generation. Anybody could jump in for a tutorial why that likely is?

Think voltage levels. What is the highest voltage I/O
standard that a south bridge has to support? An older
process is better able to support 2.5, 3.3, or even 5 V
compatible/tolerant I/Os.