Replies to post #15213 on Advanced Micro Devices Inc (AMD)

[sgolds]

kpf, how well it integrates with x86 processors depends on this part:

The ClearConnect bus is a packet switched network that provides high bandwidth and low power consumption, supporting multiple concurrent transfers giving even higher aggregate bandwidth.

What other packet switching busses are there? Hmmm...

Reading their documentation, the bus really isn't well defined. If it is based on HyperTransport, then fitting it alongside Opteron would be very simple. I don't think so, though, because of this statement about their reference board -

The board will support one or two CS301 processors. If two processors are installed, they are connected in a daisy chain via the ClearConnect bus bridge ports. One end of the bus is connected to an FPGA which implements the memory and host interfaces. The other end is brought out to an expansion connector.

http://www.clearspeed.com/downloads/overview_devboard.pdf

Doesn't really sound like HT.

They also say that the technology is available as core logic, but I think the intent is to translate a ClearConnect to either an Intel Northbridge or an AMD HT. This would be a little kludgy, it would be a whole lot cleaner if ClearConnect follows the HT standard.