i don't know about forster river. do you have more info on that chip?
intel has a history of providing functionality on a device driver running on the host that others choose to implement in asics or embedded controllers. i suspect this is another example of this. the asic on the robson board is probably simply a pci-e interface to the parallel interface of the nand device and likely includes some buffering to make the burst transfers more efficient.
i doubt if the wear leveling algorithm is all that heavy for a core2duo.
pure speculation on my part however. we'll likely know more in q1 (probably late) when it's launched.