Replies to post #35858 on Intel Corp (INTC)

[kpf]

Many thanks, Alan.

Chipguy elaborated to me on another thread on it, but clearly indicated the effect would only be relevant well beyond 45nm, so there must be another reason. In particular in Layer one. :)

I was thinking it could have to do with the nasty damascene effects AMD has run into at its 130bulk node, that's why I asked if Intel has Al in its interconnects.

If you allow some spin for the fun of it, maybe Intel could avoid the problem finding a way to avoid one level of interconnect altogether. They are quite good at making things as good as they believe is enough - and this as cheap as possible. Occasionally they err on the former one, but barely on the latter one.

K.

[chipguy]

Chipguy was explaining earlier that it is getting harder to hit the tight pitch metal layers with copper, so folks are moving to Al for M1...
No news on what INTC is doing at 45nm in this regard.

No that isn't quite what I said. The problem is that with
copper interconnect metal is surrounded by a barrier layer
to keep the copper from diffusing into the silicon. The
thickness of this barrier doesn't scale with feature size
well so the narrow lower level wires have less and less
copper at their core as feature size shrinks which drives
up effective resistivity. At some point aluminum becomes
better for the lowest level(s) of interconnect because its
resistivity is less than small cross section copper wires
which are have nearly as much barrier material as copper.
There are a few other effects like electron scattering off
the barrier/copper interface which make it even worse
than a simple cross section area ratio would suggest