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CombJelly

12/08/06 10:21 AM

#5781 RE: kpf #5780

"There might be compelling reasons to do it anyway. "

If I were to guess, it has to do with bumping the die. Maybe the result can more reliably be attached to the chip package.

chipguy

12/08/06 10:52 AM

#5782 RE: kpf #5780

Al and Cu in the same fab is not exactly what you want in the first place. There might be compelling reasons to do it anyway.

Yes there is and aluminum will likely be used again for local
interconnect (i.e. lowermost metal layers) as process feature
size shrinks.

The problem is the barrier layer for copper doesn't scale down
as fast as metal minimum width and spacing. This means as
copper wires scale down their resistance goes up faster than
basic dimensions would dictate because their copper core is
less and less of the total wire. For very small wires this closes
the conductivity gap with aluminum. The lowest metal layers
have the tightest geometries so it is where copper loses its
effectiveness fastest.

The intermediate (middle level) and global (upper) wires will
still be copper because of lower RC delay and much better
ability to carry high current reliably.

That being said, AMD probably has other reasons to use an
Al layer at 65 nm because this scaling effect will likely only
really start to bite at perhaps 32 nm and below.




KeithDust2000

12/10/06 5:11 PM

#5821 RE: kpf #5780

Klaus, On a sidenote, I like the idea of this board.

Hi Klaus,

good to hear and nice to see you posting again!

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Dell backpedals on AMD

http://uk.theinquirer.net/?article=36232