- high speed I/F needs new ATE investment; likely source
of non-trivial parametric yield loss
Could you pls enlight me what that means?
High speed interchip interfaces like HT contain sophisticated
circuitry to extract clock and data from its input receivers.
This generally means at least one DLL or PLL. In addition high
speed interface receivers and transmitters generally have tight
tolerance for output impedance, slew rate, and termination
impedance and this requires auxillary circuitry to detect and
compensate for processing variation as well as time variation
in device operating temperature and voltage. There may also be
requirements for pre or post emphasis (signal massaging) of the
transmitted/received data to counter act channel attenuation
and intersymbol interference.
All of this means there is a fair amount of mixed signal and
analog circuit content to these interfaces. This means there
will be a lot of AC and DC specs that have to be tested for
each separate instance of the interface and this adds to test
time and therefor test costs. In addition, this circuitry is
often sensitive to analog process parameter variation (changes
in transistor absolute strength, variation in ratio of strength
of n and p transistors, variation in resistance of active and
polysilicon layers and so and so on). Normal process variation
that a digital circuit can shake off and still operate in spec
can cause an analog circuit to function but not at a sufficient
level to meet all AC and DC specs. That is what I mean by
parametric yield loss.
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