Replies to post #22135 on Mosaic ImmunoEngineering Inc (CPMV)

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The appeals court affirmed claims construction part which says when referring to a key attribute of the 336 oscillator "and whose frequency is not fixed by any external crystal.” is tough to see how PTSC gets past that.

All PLLs use a reference crystal to stabilize the frequency of the on chip generated signal. In Magar the actual specific frequency of the off chip crystal was the actual frequency fed directly to the on chip and used to clock the chip. In the 336 patent the on chip oscillator generates a frequency which is then stabilized using a formula derived from the frequency of the off chip crystal. If there is a deviation from the formula a voltage increase or decrease is sent to the on chip oscillator to increase or decrease its speed until it is "locked" with the crystal generated formula. Is this considered the "same difference" I do not know. One thing is for sure and that is PTSC argued very hard to keep that wording out of the CC and the appeals court affirmed it. The reason I imagine is that the subject matter can be so confusing to the non expert jury and judges.

So the new claims construction is no crystal FIXING the frequency of the on chip oscillator. Is regulating or controlling it using a derivative of the frequency of the off chip crystal actually FIXING it? Is FIXING it an exact frequency match to the crystals frequency?

Below is the definition of a PLL which all the accused products use from Wikipedia. Basically the PLL synthesizes a frequency:

"Phase-locked loops with frequency dividers[edit]
A phase-locked loop (PLL) uses a reference frequency to generate a multiple of that frequency. A voltage controlled oscillator (VCO) is initially tuned roughly to the range of the desired frequency multiple. The signal from the VCO is divided down using frequency dividers by the multiplication factor. The divided signal and the reference frequency are fed into a phase comparator. The output of the phase comparator is a voltage that is proportional to the phase difference. After passing through a low pass filter and being converted to the proper voltage range, this voltage is fed to the VCO to adjust the frequency. This adjustment increases the frequency as the phase of the VCO's signal lags that of the reference signal and decreases the frequency as the lag decreases (or lead increases). The VCO will stabilize at the desired frequency multiple. This type of PLL is a type of frequency synthesizer."