It's also very unlikely to be incorporated into 65nm products. This process was defined long before the Z-RAM agreement, and they won't be able to manufacture it without augmenting the right process hooks.
I disagree. The trend in embedded DRAM is towards memory
IP that can be built in generic logic processes. You can build
DRAM in just about any logic process by using a 2T or 4T cell.
For a large enough block it will have a bit density up to about
twice SRAM but will be much less dense than DRAM based
on a true 1T cell which requires special processing.
AFAICT ZRAM uses floating body capacitance in a plain
SOI logic process to create a 1T cell DRAM equivalent.
Obviously there is a lot of negative trade-offs doing this
compared to a DRAM/eDRAM process with a special high
density trench or crown storage capacitor and low leakage
transistors. The amount of charge stored in a ZRAM cell
will be relatively small and the access transistor leaky
and inefficient. This is acceptable for some ASIC/MPU
applications because you aren't trying to build 512 Mb
DRAMs for $5 so you don't need very high cell efficiency
or every last fC of charge usable.
I think Prudential just demonstrated their ignorance by expecting this technology in a mid-2007 product line.
The Prudential report is highly ignorant but mainly in the
way they assess the impact on AMD products. DRAM is
like a nuclear reactor - it really becomes wildly inefficient
and unweildy compared to alternatives when you scale it
down in capacity. When you want it, you want to use lots
of it. AMD is definitely not going to use ZRAM to make
1MB L2s smaller in size. :-P
News 
Market Data 
Discover 
AI
