Replies to post #136463 on Intel Corp (INTC)

[ibc]

According to Wikipedia, Cortex-A15 has 15-25 pipeline stages. That's about the pipeline depth of Intel's "Hyper-pipelined" Willamette architecture.

I know but that table is sort of misleading. It's 17 stages (branch mispredict latency) which is usually what's quoted for pipeline depth. They add on 8 more clocks for the FP pipeline which people normally don't count.

WMT / Northwood were 20.
Prescott was 31 stages.

Keep in mind that those designs were in 180nm to 90nm - I know, I worked on them :)

The A15s are several process generations ahead.