Will soon? This sort of thing has been going on for quite a while already and the main thing TSMC itself would be worried about now as far as 16FF+ is concerned is their yield and ramp.
The timeline is like two years before production they have to have the EDA companies in to start implementing the design rules in their software and introduce early adopters to the process. During the year before they have risk production where they have early tape outs of various IP and designs and fix problems in the design rules and process and make sure their characterizations are okay.