SSE2/3 is a 128 bit SIMD architecture. Each 128 bit word can hold either 4 single or 2 double precision FP values in packed format.
The new system can apparently perform a packed SSE instruction every cycle, i.e. two 64 bit adds or two 64 bit multiplies. I can't remember if SSEx has a parallel FMAC capability but that would bring it up to 4 DP FLOP/s cycle, twice the FP capability of K7/K8 (one 64 bit add plus one 64 bit multiply every cycle).