Replies to post #8678 on Rambus (RMBS)

[calbiker]

Re. CAS latency post

About 4 weeks ago someone listed the claims going to trial. If that list is correct, then stk_hawk's list is incorrect. It's extremely dangerous to conduct a patent search using 'rambus' and the last 3 digits of the patent. Some Rambus patents have the same last 3 digits. Looks like he has the wrong '916 patent listed. His conclusions are as well quit iffy.

Here's all 10 claims. Included is cal's guess what invention the particular claim represents.

5,915,105 June 22, 1999
Integrated circuit I/O using a high performance bus interface

On-chip DLL
34. The memory device of claim 31 further including clock receiver circuitry to receive the first external clock and wherein the internal clock generation circuitry includes delay locked loop circuitry, coupled to the clock receiver circuitry, to generate the first internal clock signal and the second internal clock signal using at least the first external clock.

6,034,918 March 7, 2000
Method of operating a memory having a variable data output length and a programmable register

Programmable CAS latency register
24. The method of claim 18 further including storing a delay time code in an access time register, the delay time code being representative of a number of clock cycles to transpire before data is output onto the bus after receipt of a read request and wherein the first amount of data corresponding to the first block size information is output in accordance with the delay time code.

On-chip DLL
33. The method of claim 18 further including generating at least one internal clock signal using a delay locked loop and the external clock signal wherein the first amount of data corresponding to the first block size information is output onto the bus synchronously with respect to at least one internal clock signal.

6,324,120 November 27, 2001
Memory device having a variable data output length

Precharge
33. The memory device of claim 29 wherein the first operation code includes precharge information.

6,378,020 April 23, 2002
System having double data transfer rate and intergrated circuit therefore

Synchronous memory operation
32. The integrated circuit device of claim 31 wherein the input receiver circuitry receives address information synchronously with respect to the external clock signal.

Synchronous memory operation
36. The integrated circuit device of claim 35 wherein the clock alignment circuit generates an internal clock signal, and the output driver circuitry outputs data in response to the internal clock signal.

6,426,916 July 30, 2002
Memory device having a variable data output length and a programmable register

Precharge
9. The method of claim 1 wherein the first operation code includes precharge information.

Programmable CAS latency register
28. The memory device of claim 26 wherein in response to a second operation code, the value is stored in the register.

On-chip DLL
40. The memory device of claim 26 further including delay lock loop circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal, wherein the plurality of output drivers output the amount of data in response to the internal clock signal.

6,452,863 September 17, 2002
Method of operating a memory device having a variable data input length

Synchronous memory operation
16. The method of claim 15 wherein the first amount of data is sampled over a plurality of clock cycles of the external clock signal.