Wednesday, February 22, 2006 12:27:39 PM
http://www.reed-electronics.com/electronicnews/article/CA6309431.html
"TSMC: Immersion Litho Nearly Production Ready
Online staff -- Electronic News, 2/22/2006
TSMC today revealed that its immersion lithography program has produced test wafers well within acceptable parameters for volume manufacturing.
"Our goal is always zero defects," said Burn Lin, senior director of TSMC's micropatterning division, in a statement. "Recently, TSMC produced multiple test wafers with defects rates as low as three per wafer -- better than any other immersion results to date, and comparable to the very best dry lithography results. With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing."
Immersion techniques...
...TSMC's immersion lithography technology is targeted at the foundry’s 45nm manufacturing process.
The findings of TSMC’s tests will be revealed tomorrow by company researchers at the SPIE Microlithography Conference in San Jose."
Not 32nm, granted, but immersion nonetheless.
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