SAN JOSE, Calif. — Overcoming manufacturability challenges at the 45-nanometer node and beyond requires a migration to more "regular" design layouts, according to Luigi Capodieci, principal memer of Advanced Micro Devices Inc.'s technical staff.
Presenting a paper at the SPIE Microlithography Conference here Tuesday (Feb. 22), Capodieci argued that irregular features within designs works against automated "layout printability verification" in an age where process variability has become prevalent.
More and more, Capodieci said, yield ramps can be accelerated by using regular, standardized circuits and features..."
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