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Re: chipguy post# 70801

Friday, 02/17/2006 6:50:16 AM

Friday, February 17, 2006 6:50:16 AM

Post# of 97570
Chipguy, iirc K7 was designed for two levels of cache although only one level was first implemented.

Although as you say AMD currently doesn't have the fab capacity add moster L3 caches on mainstream volume products fab capacity is expanding at a rather steep pace this year (fab 36 ramp + Chartered fab 7) and will allow reasonable sized L3 caches (like the 4MB the Inq mentioned yesterday) in FX and Opteron lines even if on 90nm.

Wow 7ns 12MB L3 is incredibly fast. That isn't what Itanium is using though, is it?

Regards,

Rink


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