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Re: chipguy post# 24991

Tuesday, 02/14/2006 12:37:01 AM

Tuesday, February 14, 2006 12:37:01 AM

Post# of 151836
chipguy,

You also seem very confused about binning. It costs
the same to make a low bin, mid bin, and high bin
MPU. The difference is what you can sell them for.


That is, if you can sell them at all. If only half bin at the clock speed and power consumption that you can sell, your costs double.

It is highly unlikely that chipsets bin below one bin that Intel sells, It is very likely that a number of CPUs bin either below required clock speed, have higher than desired leakage or both.

Another problem is that if the center of distribution of your bins is too low, yielding next to nothing of the highly desired high end bins, Intel needs to aggressively tweak parameters that in fact produce some of the higly desired bins, but that is done at expense of yields. No such problems exist with chipsets.

Depends on the relative area, process, package, and
test particulars. A 100+ mm2 northbridge chip made
in 130 nm and packaged in a 1000+ I/O BGA might
cost Intel more to make than the 83 mm2, 130 nm
Banias P-M.


Today? Yes. But at the time Banias was the high end state of the art CPU, the costs were much higher. The reasons for that were steep depreciation of the capital expenses, immaturity of the process, the need to bin the CPUs above the threshold that would produce high yields.

It has been a long time since Intel was cruising with greatly binning high yielding Northwood...

Anyway, my comparison was of today's CPUs and today's chipsets, not today's chipset vs. CPU two process nodes back.

Joe


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