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[Chris McConnel]

Intel to go four-core in early 2007


News reports are hitting the wires that Intel plans to release a four-core processor for two-socket systems in late 2006 or early 2007. The quad-core chip, codenamed Clovertown, will bring lower end systems into the eight-core realm. A later quad-core chip, codenamed Tigerton, is planned for higher-end four-socket systems.

The accelerated introduction of a quad-core design will put Intel on track to match AMD in the all-important "number of cores per chip" metric that is replacing GHz as a single, consumer- and press-friendly number that can be easily used for meaningless horserace-style comparisons. You can get a taste of that in the coverage at SFGate and Reuters. The Register, on the other hand, calls it correctly in pointing out that Intel's much delayed next-generation frontside bus, called CSI, is MIA for 2007.

As I pointed out in a post on Intel's major 2006-2007 weak spot, these four-core processors will be crammed into a socket that's fed by an out-of-date front-side bus. This bandwidth problem will be exacerbated by the fact that Intel still won't have an on-die memory controller, which means that memory traffic will be flowing to all four cores over that single, dated FSB. It's not pretty, and it won't be fixed until sometime in 2008. This will give AMD plenty of time to leverage HyperTransport and the Athlon64's on-die memory controller to maximum advantage in the server market.

When both AMD's and Intel's quad-core chips first come out and are benchmarked against each other in real-world systems, I think it's a safe bet to say that the AMD machines will outperform the Intel boxes on bandwidth- and memory-intensive server tasks. This is a shame, because Intel's core architecture is by all accounts fantastic. (We'll know for sure when Merom comes out.) To have it hobbled by these kinds of system-level design missteps is unfortunate.


http://arstechnica.com/news.ars/post/20060211-6160.html