Advanced Micro Devices Inc (AMD)

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Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said.

AMD, in another shot at Intel, establishes powerful 64-bit platform
By Mark Hachman, Electronic Buyers' News
Oct 5, 1999 (7:58 AM)
URL: http://www.ebnews.com/story/OEG19991005S0014

Taking another step away from Intel Corp., Advanced Micro Devices Inc. today disclosed a powerful, internally developed 64-bit microprocessor architecture and complementary bus design. Once known as a manufacturer of cloned Intel chips, AMD must now be considered a true alternative supplier to Intel. AMD will debut its “X86-64" architecture today at the Microprocessor Forum in San Jose, complemented by its Lightning Data Transport (LDT) I/O architecture. AMD executives also announced that they're considering the so-called K6-2 Plus, a K6-2 chip with integrated cache that takes advantage of the company's new 0.18-micron process, as a complement to the Athlon Ultra workstation/server chip the company plans to ship next year.

AMD's first 64-bit chip, named "Sledgehammer," is expected to ship in 2001, company executives said.

AMD's "X86-64" design represents an evolutionary approach. In fact, AMD has emerged as the standard-bearer for the X86 instruction set that Intel developed. Intel's 64-bit architecture, now called Itanium, is a completely new infrastructure.

"The key here is that it's a simple change," said Stephen Lapinski, director of product marketing at AMD's Computation Products Group in Sunnyvale, Calif.

Following years of catastrophic manufacturing flubs, AMD has set out to ensure that manufacturing the new chip will be the easiest piece of the puzzle. Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said. While AMD's timetable still calls for 0.18-micron manufacturing to begin at Fab 30 in Dresden, Germany, later this quarter, the company yesterday showcased an 800-MHz Athlon running on the new process.

More importantly, AMD claims that the combination of a small die size and its 0.18-micron process will allow the company to pack more than one 64-bit X86 microprocessor on a single die. That's important, given the fact that X86 integer instruction performance is closing in on RISC chips, Lapinski said. Through IEEE-compliant, triple-operand, double-precision floating-point instructions that AMD is designing for the new architecture, the company hopes to eliminate the floating-point advantage of RISC chips as well, he said.

Other chip designers do maintain some level of X86 compatibility. Intel's Merced microprocessor contains an X86 instruction unit, in addition to the 64-bit architecture. Compaq Computer Corp.'s 64-bit Alpha uses FX!32 binary translations and emulations to translate X86 code into its own and native instructions, while Sun Microsystems Inc. pairs an X86 SPARC core on a single add-on card. But in each, X86 instructions are relegated to second-class status, Lapinski said.

When pairing more than one microprocessor on-chip, AMD will use undisclosed custom logic to manage the infrastructure. Off-chip, however, AMD has designed the custom LDT bus for I/O and coprocessor chips. The LDT is a bidirectional bus, either 8, 16, or 32 bits wide; the bit width is negotiable at the device's initialization. Data passes through multiple logical channels in up to eight links or bridges, which can be connected to several daisy-chained devices. Lapinski declined to further discuss AMD's coprocessor strategy.

Lapinski also said he realized that there was far more to the 64-bit issue than simply designing a winning chip. "One thing we haven't brought up is the software infrastructure," he said, noting that Microsoft Corp. and Compaq have crossed swords over Windows NT support for Compaq's 64-bit Alpha microprocessor. "We don't think [OS support] will be a problem," he said.

AMD executives thought minimizing the infrastructure changes would be of benefit to OEMs. "Intel took the Merced design and forced it on [the OEMs], said Bob Mitton, division marketing manager for AMD's workstation products.

Intel executives see things a bit differently. "The bottom line is we have full X86 compatibility," said Ron Curry, director of marketing for IA-64 products at Intel, Santa Clara, Calif., who compared AMD's approach to souping up a Volkswagen with wider tires and a faster engine.

At one point, analysts speculated that the Alpha would be AMD's entry into 64-bit computing through the "Slot B" connector that both companies used. That has apparently changed. "We're not going to pursue the direction of Slot B," Lapinski said. However, Alpha Processor Inc. and start-up HotRail Inc. are expected to be the main chipset suppliers, although that does not necessarily exclude Reliance Computer Corp., he said.

AMD also disclosed further details about its 32-bit-microprocessor strategy. Next year, the Athlon Ultra for workstations and servers will feature 1 and 2 Mbytes of off-chip, full-speed, 16-way, set-associative Level 2 cache. While AMD executives declined to discuss clock speeds, Lapinski did say that the EV-6 processor bus will run at 266 MHz, faster than the 200-MHz bus conventional Athlon chips employ. Related chipsets will feature 66-MHz, 64-bit PCI with 4X AGP Pro connections and a PC 2100 DDR DRAM interface.

Lapinski also said AMD is evaluating the so-called K6-2 "Plus," a 0.18-micron K6-2 reported to include 128 and 256 Kbytes of on-chip cache. A third chip without Level 2 cache is also thought to be under consideration, although Lapinski would not divulge details. "When the K6 hits 0.18 micron, there's a couple of things that make sense," he said. "There's a possibility that we'll have more to tell you about what's coming down the pike in the fourth quarter," he added, possibly at the Fall Comdex trade show in Las Vegas..