A method for converting a hardware description language describing an integrated circuit or software operating thereon to an alternative programming language, such as ANSI C, C++, Java, or other object-oriented programming language, is described. The method provides for the single compilation operations as well as the ability to link multiple compilations to simulate large hardware description language designs. The method of the present invention improves the run time efficiency of the compiled code in a more user-friendly format.
A Hardware Description Language (HDL) is the type of computer language that FPGA simulations are written in. Examples are Verilog and VHDL. This patent application appears to be for a method of better simulating the HDL on a PC. Interesting...
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