Another article with opposite perspective
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Intel: Jefferies Sees Advantage in Mitigating Transistor ‘Leakage’
By Tiernan Ray
Jefferies & Co.‘s Mark Lipacis today reiterated a Buy rating on shares of Intel (INTC), and a $30 price target, writing that Intel’s advantage in semiconductor process technology is set to expand as the issue of so-called leakage power becomes more prevalent with smaller chip feature sizes.
Lipacis paints the implications of leakage, and how they require Intel’s “more-efficient” transistor designs:
The power consumed by a transistor or digital integrated circuit (digital IC or chip) can be broken into two groups: 1) Leakage Power, or power used by a transistor when it is idle; and, 2) Dynamic Power, or the power used when the transistor is turned on. Historically, power consumption was driven by the power consumed by the transistors on the chip as they were being used (dynamic power). However, as chips have gotten smaller, so have gate widths, pitch and insulators. And as those (electron) barriers become thinner, the probability that electrons break through those barriers (aka “tunnel” in quantum physics) increases. That dynamic is known as leakage. As the process nodes (and transistors) have become smaller, the amount of leakage power increases exponentially. We think that high leakage power in transistors has the potential to shift the competitive dynamics in favor of Intel’s core competency of transistor design. Before, when power consumption was driven more by dynamic power, architectural considerations like instruction set architecture (ISA: RISC vs CISC), and microarchitecture simplicity (e.g., instruction size, number of memory registers) etc., could have a material effect on the power consumption of the entire chip. However, if more of the power consumption of the chip is being driven by transistors that are idle, then we think that more efficient transistor design becomes more critical. And we think that Intel has consistently delivered innovation in transistor design that has kept it ahead of its competitors.
Lipacis notes that Intel spent $60 billion building factories and funding R&D in the last three years, double the $30 billion spent by Taiwan Semiconductor Manufacturing (TSM), the contract foundry that manufactures chips for Intel competitors such as Qualcomm (QCOM).
He also notes Intel has had several breakthroughs contributing to power efficiency in chips, such as “strained silicon” technique, in 2003, “high-K metal Gate” in 2007, and the latest, Tri-Gate 3-D transistors, which were first unveiled in 2011 and are now in mainstream production.
Pointing to a slide used by Intel at a Jefferies conference, he notes the company inserted the phrase “wait and see” regarding the next innovation, due this year. Lipacis wonders if Intel may tomorrow unveil that new breakthrough at its annual analyst day event at its headquarters in Santa Clara.
Intel shares today closed down 14 cents, or 0.6%, at $24.56.
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