EW, others: Semiconductors 101
I will try to lay out my understanding of what is necessary to go from here to a shipping product.
First, let's look at where we are. We have a product that consists of basically a computer program. Now let's look at where we want to be. We want to have a volume produced Application Specific Integrated Circuit (ASIC). Actually, where we are and where we want to be are not that different conceptually. In concept, our product will take a digital signal, turn it into a signal that will travel fast and far over copper lines, and turn it back into a digital signal at the other end. The current prototype performs all of these functions on a computer. The software tells the computer how to modify the signal. The final product, an ASIC, does almost the same thing, but instead of having software tell a computer what to do, an ASIC is basically a computer with the software hard-wired into it. It is sort of like the ROM in your computer. The Basic Input Output System (BIOS) that makes your computer start, self-test and run before windows loads is similar in concept. It contains software instructions that are hard-wired onto a chip.
The software prototype was developed using special software that is specifically designed for eventual transition to an ASIC. Each command on the programming language simulates a physical transistor layout and as such, each command could be theoretically easily translated into part of an ASIC design.
The process of taking the computer program and making an ASIC design from it is called mapping. In the mapping process, the computer program is broken down into its individual commands, and each command is assigned a transistor layout that will become part of the ASIC. As I said above, in theory, it is simply a matter of mapping all of the program commands to transistor layouts, connecting them, and you have a good ASIC design.
However, in practice, it is not that easy. There are several complications that can emerge if the number of lines of code gets very large, and if the device needs to operate at high speeds. When you start talking about millions of lines of code for devices that must operate at over 100MHz (which you would need to do if you want to transmit 100Mbps)the complications in mapping become huge. The biggest problem becomes layout. In a computer program, there are functions, sub-routines, etc. that are discrete parts of the code and are jumped in and out of during program flow. These discrete parts can reside anywhere in the program flow as long as the "gosub" and "return" pointers tell the program flow where to go. To put these routines into an ASIC design, the locations of the corresponding transistor layouts become critical. You cannot necessarily lay them out in the same order that they appear in the program. They need to be physically placed so that interconnects are short as possible. Additionally, interconnects (basically tiny wires a few atoms thick) that connect the different parts of the ASIC must be carefully routed so that timings are correct. In a high-speed silicon device, the speed of a signal from its point of origin on the chip to its destination on the chip must be taken into account in the design so that all signals leave and arrive on a "tick" of the internal clock. This is a very difficult problem to solve, and gets more difficult as the speed of the device increases.
Another problem is heat. Even if you have a perfectly designed ASIC, you still have to test it for hot spots, particularly for high-speed devices. Such devices can heat up as fast as 100 degrees per second, and if there are spots on the chip that are much hotter than others, the chip can self- destruct.
Another problem is physical layout. To understand this problem, consider that a chip is a two-dimensional device. You cannot have interconnects cross each other. They must go around each other. Sometimes, the layout demands that interconnects must cross. Since it is not possible to cross interconnects without shorting them together, you basically have to add another plane or layer. Think of layers as floors in a building, and the interconnects as the hallways. The hallways must never cross, and because of that, there will be times when you must take an elevator up or down to another floor and then navigate the hallways and then take the elevator back again to get where you want to go without crossing a hallway. Complex chips can have as many as 7 or 8 layers.
All of these things have to be done when mapping the ASIC. Of course, there are optimizing tools that can help, and the process is largely computerized. However, it is an extremely complicated process and requires a lot of tweaking for complicated designs to get it right. Going from the code we have now to a completed ASIC design will take several months. Throw piles of money at the problem and you can pare that down to several weeks. Of course, you have to have piles of money.
OK. So now you have a completed ASIC design. What do you do now? You fab a chip. But this is no ordinary chip. It is a very complicated and high speed device. You can't just go down to Joe's Chip Shop to get it made. Because of its complexity, it will need to be made on state-of-the-art processes. I would guess that we would need to use a Fab with the capability to use 180nm design rules at the least. This means that the interconnects and other lines are at most 180 nanometers wide. This is a very complicated process, and will probably require at least 2 "spins" before a production design is taped out. The Fab knows how to take an ASIC design on a computer disk and create all of the tools, masks, etc. necessary to produce it. However, there is no way to know of the product will work as designed. So, you do a "spin" (jargon for producing a run of chips of a given design) to make some test chips. Then you test the chips, find problems, and tweak the design or process again. Typically, you will do at least 2 spins before you have the process right. Each spin takes at least 6 weeks. Even Intel can't go any faster than that.
So, there you have Semiconductors 101. As for this question:
I contend that there is NO WAY a company would put an order in for massive amounts of chips without having an actual hardware chip (FPGA) to test first.
I agree. We will not see any orders until we have engineering samples of the final product (typically taken from the 2nd or maybe 3rd spin)in the hands of the customers. A good target for the first of the year 2004.
I know that the RAQ said something about four months to turn out an ASIC. Wait.... Here it is:
Once we place an order with a semiconductor fabricator, we would expect to receive the finished chips in a maximum of four months, although we have been encouraged by discussions with a number of fabs overseas that are capable of turning around an order in a much shorter period of time.
This statement is a bit misleading. We would never place an order with a Fab without a completed ASIC design. This statement completely neglects the mapping process. So, assiming that we have a completed ASIC design (which, remember, will take several months to map) we give the design to the Fab. They spin one stepping (6 weeks), we evaluate the samples (2 weeks), and everything is perfect, then it takes 6 more weeks for production chips to start rolling off of the line. So, 3-1/2 months is about right if everything goes perfectly. Everything won't go perfectly. I figure at least 6 months from completed ASIC design to final product. Add that to the 4 months or so to map the ASIC design, and you get the 10 months that I conjectured in my last post.
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