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Tuesday, April 08, 2003 2:59:32 AM
additional pipeline stages should have added to the frequency.
Good argument if the Hammer *was* a K7 with 2 more pipe stages. But it isn't. The extra
pipe stages are in the front end which have been significantly reorganized to 1) raise IPC
by reducing structural hazards etc, and 2) to handle yet another layer added to the instruction
set. These changes could very well use up most of the logic eval time of the extra two pipe
stages. FWIW my own WAG is Hammer will eventually make it to 2.4 GHz , may be a bit
higher.
I gave you an example of Intel adding a memory controller to their CPU core plus a
graphics controller and seeing no speed degradation whatsoever compared to their
mainstream cpu.
Why would you ever expect speed degradation? What critical processor timing path
would run through a peripheral?
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