Advanced Micro Devices Inc (AMD)

[chipguy]

IBM also seems to be saddled with an SOI process that, at the 0.13 micron level, cannot
get speeds beyond 1.4 or possibly 1.8 GHz for their Power4/5/Apple products.

That is an over simplification. The Power4 processor family used a design methodology
much closer to an ASIC flow with embedded memory than the full custom design flow
used by Intel, HP, and others.

I have talked to circuit designers on a high end uP design team (non-IBM) about their
experience with IBM's bulk and SOI processes. If you redesign all your circuits from
the ground up, and you know what the hell you are doing, then you can realize 10 to
15% higher clock rates with SOI (IBM claims higher speed ups but they use much
less dynamic logic than other design teams and thus start from much further behind).

The thing most people don't realize in these SOI vs bulk religious wars is there isn't a
one size fits all solution. It is not a contradiction when Intel says it can best meet its
goals at say 130 nm with bulk CMOS while IBM says SOI is just the ticket at 130 nm.
The difference is in manufacturing volume. Intel makes so many chips that engineering
costs are spread out thinly and manufacturing cost is a major chunk of overall chip cost.
For IBM, its Power4 chips are manufactured in such small numbers that even if SOI
doubles the silicon cost of each uP that it is still far less expensive than an extra $100m
in design effort and speed path tuning respins (especially for a server chip that has an
long and expensive verification and requal).