Advanced Micro Devices Inc (AMD)

[chipguy]

TIA for any clarifications/explanations

The "magic memory" I spoke of isn't so much zero latency memory as the removal
of the non-cache memory component of CPI. That not only removes latency overhead
but also bank conflicts, page misses, precharge delays, cache line burst transfer time,
address and data setup time, internal transfer time, and memory controller overhead.
That is why I called it magic memory, not just zero latency memory.