Intel Corp (INTC)

[chipguy]

I would be willing to bet that the improvement in throughput from Crusoe to Astro will be in the neighborhood of 50% on a constant-clock basis.

The performance gain from 2 to 4 way issue OOO
execution superscalar RISC was about 50%.

With ILP diminishing returns and the problem
of memory stalls in an in-order machine, going
from 4 to 8 way issue VLIW will not come close
to 50% speedup.

If the Astro is architecturally 50% faster than
Crusoe, which I doubt, then most of the speedup
would come from other, quite substantial, design
enhancements unrelated to issue width.