Advanced Micro Devices Inc (AMD)

[chipguy]

The important point for latency is how many hops to the processor
holding (or hosting) the cache line and how many hops back.

That's how it works in an EV7 box but the Opteron doesn't use a distributed
directory based coherence scheme like the EV7 does. How will an Opteron
wanting to access a section of memory know which other Opteron(s) have
that memory cached until it has waited for a potential reply from the Opteron
in the system furthest away in terms of round trip delay?