From the website. This seems to say that work on the FPGA also includes coversion features for the ASSP. This would constitute some level of work on the ASSP if correct.
Manufacture in the form of a finished chip (which will require additional engineering)
During this interval between the release of the FPGA and the release of the finished chip, we will wish to fine-tune our computer coding and system design. Accommodating the needs of our prototype customers, the industry standards bodies, and further innovations on our part would be the types of drivers that could cause us to fine-tune our designs. Of course, we would like to believe that we won't have to make changes to our software and designs during this phase, but it would be absolutely typical for changes to be made prior to committing the design to final silicon. Our design team is planning for the FPGA-to-ASIC phase by incorporating conversion features into our design now. Rim Semi is now in preliminary discussions with chip manufacturers on costs and time to market and will provide you with an update from time to time as the status of those business arrangements.
