Saturday, March 29, 2003 9:14:34 PM
What I find downright shocking is the low clockspeed of Itanium. This is a simple in-order chip design, basically 3 DSP cores on a piece of silicon with some cache added. All the hard work has been pushed off onto the compiler (which is why it is so incredibly fussy about tweaks to the code).
Being a simple, in-order design, Itanium should clock higher than P4. What's up the 1ghz limit on .18? (P4 did 2ghz).
And Itanium is only supposed to make it to 1.3ghz on .13 while P4 is going to 3.2ghz, maybe higher:
http://www.intel.co.jp/idf/us/fall2002/presentations/PCS061PS.pdf
What went so colossally wrong with Itanium?
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